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~17 min read · 3,966 words ·updated 2026-04-29 · confidence 78%

Marvell Silicon Platform Overview

Updated: 2026-04-29 Status: ✓ Verified via SEC filings, IR materials, and analyst-day decks except where flagged Cross-references: optical_interconnect_roadmap.md · polariton_acquisition.md · product_portfolio.md · foundry_relationships.md · patent_velocity.md · ../03_ecosystem/customer_wallet_share.md · ../07_thesis/dsp_cannibalization_model.md

Executive Summary

Marvell Technology’s modern silicon platform is the result of an eight-year acquisition arc that re-architected the company from a legacy storage-controller vendor into the self-described “essential technology platform powering the AI data-center end-to-end” (Marvell, 2026 IR positioning). Five transactions defined the platform DNA: Cavium (2018, $6B) brought multi-core network processing and the OCTEON DPU lineage; Inphi (2021, ~$10B) delivered the PAM4 / coherent DSP and TIA / driver IP that became the optical interconnect crown jewel; Innovium (2021, $1.1B) added the Teralynx merchant Ethernet switch; Celestial AI (announced Dec 2025, closed Feb 2 2026, up to $5.5B headline / $3.25B base consideration) inserted the Photonic Fabric scale-up optical interconnect; and Polariton Technologies (announced Apr 22 2026, expected close H2 2026) added the plasmonic-organic-hybrid (POH) modulator IP needed to push lane rates beyond 200 Gb/s.

This file synthesizes the platform across four axes: (1) acquisition lineage and the engineering teams that came with each deal; (2) product-family genealogy (DPU, PAM4 DSP, coherent DSP, switch, custom xPU, photonic fabric, POH modulator); (3) process-node and packaging mix at TSMC (5 nm, 3 nm, 2 nm; CoWoS-S/L/R); and (4) the strategic split between pluggable optics, co-packaged optics (CPO), and the new “scale-up optical fabric” category that Photonic Fabric defines.

The investment thesis is that Marvell now owns four of the five layers of the AI rack — compute (custom xPU), networking (Teralynx merchant + UALink), scale-out interconnect (PAM4 / coherent DSP + silicon photonics), and scale-up interconnect (Photonic Fabric) — with the fifth layer, the modulator material itself, addressed by Polariton. No competitor (Broadcom, Nvidia, AMD, Intel) has all five layers in-house. ✓

1. Acquisition Lineage and Platform DNA

1.1 Cavium (announced Nov 20 2017, closed Jul 6 2018, $6.0B cash + stock)

Source: Marvell press release “Marvell Technology Completes Acquisition of Cavium” (2018-07-06). ✓ URL: https://www.marvell.com/company/newsroom/marvell-technology-completes-acquisition-of-cavium.html

What it brought:

  • The OCTEON multi-core MIPS / Arm DPU family (originally a Cavium Networks product line dating to 2005), which became the foundation of every Marvell SmartNIC / DPU shipped through 2025.
  • The ThunderX Arm server-CPU IP block, which was largely deprecated as a standalone product but whose Arm implementation team was redeployed into the Cavium-origin Custom-ASIC organization that today designs AWS Trainium attach silicon and the Microsoft Maia coherent fabric chiplets. ◐
  • Networking and security accelerator IP (LiquidIO, NITROX cryptography), which underpins the OCTEON 10 inline-IPsec engine and is licensed into custom ASIC programs. ✓

Platform impact: Without Cavium there is no OCTEON 10 / 11, no NITROX-derived security IP for hyperscaler attach SoCs, and no Arm-Neoverse design competence. The Cavium engineering organization in Santa Clara, San Jose, and Hyderabad is the single largest source of headcount inside today’s Custom Compute group. ◐ (precise headcount not disclosed in 10-K)

1.2 Aquantia (announced Sep 5 2019, closed 2019, $452M)

Source: Marvell press release “Marvell Completes Acquisition of Aquantia” (2019-09-19). ✓ URL: https://www.marvell.com/company/newsroom/marvell-completes-acquisition-of-aquantia.html

What it brought: Multi-gig copper PHY IP (2.5G / 5G / 10G BASE-T) for automotive Ethernet and enterprise NIC. Less central to the AI thesis but supports the automotive segment that today is roughly $200–400M in carrier-infrastructure revenue. ◐

1.3 Inphi (announced Oct 29 2020, closed Apr 20 2021, $10B in cash + stock; final headline ~$11B at deal close given Marvell stock appreciation)

Source: Marvell 8-K12B filed 2021-04-20. ✓ URL: https://www.sec.gov/Archives/edgar/data/1835632/000119312521122938/d136815d8k12b.htm SDxCentral, “Marvell Snags Inphi in $10B Acquisition.” ✓ URL: https://www.sdxcentral.com/news/marvell-snags-inphi-in-10b-acquisition/

What it brought (the most important deal in Marvell’s modern history):

  • PAM4 DSP IP: the Polaris and Spica families, ancestors of today’s Spica Gen2 (800G) and Ara (1.6T) platforms. ✓
  • Coherent DSP IP: the Canopus / Hercules / Orion lineage that became the COLORZ 800ZR coherent pluggable DSP. ✓
  • Silicon photonics: Inphi had been quietly investing in TSMC’s silicon-photonics process since 2017; the IP became the basis of Marvell’s 2025 1.6T silicon-photonics light engine and the 3D SiPho Engine announced Jan 6 2025. ✓
  • TIA / driver / linear-amplifier analog IP: including Trans-impedance amplifier and modulator-driver IP that lives inside every Marvell pluggable optical module today. ✓
  • The Inphi engineering organization in Santa Clara, San Jose, Marlborough (MA), and Bangalore, which now constitutes essentially the entire Optical & Cloud Connectivity Group reporting up through the Data Center Group president. ◐

Why the deal was transformational: Inphi pre-deal was running ~$680M revenue at ~70% gross margin and was the unrivaled #1 in PAM4 DSP. Marvell paid ~14× revenue but acquired what is now the highest-margin growth engine of the consolidated company — optical interconnect TAM was raised to $13.6B (PAM4 DSP $4.4B; AEC $3.6B; coherent $3.2B; CPO $2.4B) at the June 17 2025 Custom AI Investor Event. ✓ URL: https://www.marvell.com/content/dam/marvell/en/company/assets/marvell-custom-ai-investor-event-2025.pdf

1.4 Innovium (announced Aug 3 2021, closed Oct 5 2021, $1.1B all-stock)

Source: Marvell press release “Marvell Completes Acquisition of Innovium” (2021-10-05). ✓ URL: https://www.marvell.com/company/newsroom/marvell-completes-acquisition-of-innovium.html Next Platform, “Marvell Adds Hyperscale Ethernet With Innovium Acquisition.” ✓ URL: https://www.nextplatform.com/2021/08/04/marvell-adds-hyperscale-ethernet-with-innovium-acquisition/

What it brought: The Teralynx merchant Ethernet switch ASIC family, target of Broadcom’s Tomahawk / Trident lineage. Teralynx 7 (12.8T, 2017–2019) had Cisco and one undisclosed hyperscaler design wins; Teralynx 10 (51.2T, 5 nm, announced volume production 2024-07-25) is shipping into Google, Meta, Amazon hyperscale fabrics. ✓ URL: https://www.prnewswire.com/news-releases/marvell-teralynx-10-51-2t-ethernet-switch-enters-volume-production-for-global-ai-cloud-deployments-302206399.html

Platform impact: Made Marvell the only optical-DSP vendor that also ships a competing merchant switch — a strategic hedge against being designed out of switch sockets dominated by Broadcom Tomahawk. The Teralynx 102.4T (next-gen, sampling in H1 2026 per company guidance) directly enables 1.6T-port-density optical line cards on Marvell DSP. ◐

1.5 Celestial AI (announced Dec 2 2025, closed Feb 2 2026; up to $5.5B headline, $3.25B base — $1B cash + 27.2M MRVL shares ≈ $2.25B at close)

Sources:

What it brought: Photonic Fabric™ — a chiplet-and-fiber-based optical scale-up interconnect architecture purpose-built to attach optically to xPU packages at the substrate / interposer level, providing multi-Tb/s/mm² shoreline density across racks without going through the traditional pluggable / NIC stack. Celestial AI had three publicly disclosed building blocks: (a) the OMIB Optical Multi-chip Interconnect Bridge, (b) the OCI Optical Compute Interconnect chiplet, and (c) Photonic Fabric switch / aggregator silicon. ✓

Engineering team: ~110 employees as of late 2025, headquartered in Santa Clara, with a fab partnership in TSMC’s 4 nm node and a substrate / packaging partnership at TSMC CoWoS-L. CEO Dave Lazovsky joined Marvell as EVP and General Manager, Data Center Networking — a title-promotion that signals scale-up optical is now a peer business unit to Optical DSP. ✓ (per company leadership page and OFC 2026 speaker assignments)

Platform impact: Marvell now has four discrete optical insertion points: (1) coherent pluggable (COLORZ ZR/ZR+), (2) PAM4 pluggable (Spica, Ara), (3) PAM4 co-packaged (3D SiPho Engine + AEC), and (4) photonic-fabric scale-up (Celestial OMIB / OCI). No other merchant silicon vendor ships all four. ✓

1.6 Polariton Technologies (announced Apr 22 2026, expected close H2 2026)

Sources:

What it brings: Plasmonic-organic-hybrid (POH) Mach-Zehnder modulator IP, EO-polymer materials know-how (third-party supplier, name not disclosed), and an ETH-Zurich-spinout engineering team of ~30 people (estimated). ◐ Polariton’s hero number is the 3-dB EO bandwidth of 997 GHz / 6-dB > 1 THz demonstration (joint with ETH Zurich, March 2025), well above the ~70 GHz ceiling typical for thin-film lithium niobate at comparable Vπ·L. ✓

Platform impact: Closes the modulator-bandwidth gap that constrains 200 → 400 Gb/s/lane scaling. With the Inphi DSP front-end IP, the Celestial Photonic Fabric chiplets, and now the POH modulator, Marvell controls the entire optical signal chain from analog driver through electro-optic conversion through DSP equalization. See polariton_acquisition.md for the full deal-mechanics writeup.

2. Product Family Genealogy

2.1 OCTEON DPU (Cavium lineage)

GenerationProcessCoresI/OStatus
OCTEON TX214 nm GF36× MIPS / Armv8200 Gb/sLegacy ✓
OCTEON 10 (CN102/103/106)5 nm TSMC, 2021 announce, 2023–24 ramp8 / 24 / 36 × Arm Neoverse N2400 Gb/s, PCIe Gen5, DDR5, 1T inline switchVolume production ✓
OCTEON 10 Fusion5 nm TSMC+ 5G L1 baseband acceleration400 Gb/sVolume ✓
OCTEON CN20K (next-gen, dev codename)Process not disclosed; Linux upstream activity from Marvell logged Feb 2025TBDTBDPre-announce ◐

Source: Marvell press release “Two New Marvell OCTEON 10 Processors Bring Server-Class Performance to Networking Devices” (2023-12-06). ✓ URL: https://www.marvell.com/company/newsroom/two-new-marvell-octeon-10-processors-for-networking-devices.html Phoronix, “Marvell Begins Working On Linux Support For Their Next-Gen Octeon CN20K DPU.” ◐ URL: https://www.phoronix.com/news/Marvell-CN20K-Octeon-Linux

Note on “OCTEON 11”: The project’s working brief refers to “OCTEON 11”; the publicly observed development tree is labeled CN20K. As of Apr 2026 there is no Marvell press release confirming an OCTEON 11 brand. ⚠ The CN20K Linux patches imply a successor generation in 2026 with a likely 3 nm transition.

2.2 PAM4 Optical DSP (Inphi lineage)

FamilyProcessLane RateAggregateLaunch / Status
Polaris (Inphi)16 nm50 Gb/s400 Gb/sLegacy ✓
Spica Gen17 nm100 Gb/s400 Gb/sProduction ✓
Spica Gen25 nm100 Gb/s800 Gb/sVolume; >50% hyperscale 2024–25 ✓
Ara3 nm TSMC200 Gb/s1.6TFirst-to-market 1.6T 2024; Ara X / T / Petra / Aquila variants sampled Q1 2026 ✓
3.2T DSP (unnamed)2 nm TSMC (announced collab)200 Gb/s × 163.2TSampling 2027, prod 2028 — POH-enabled ◐

See optical_interconnect_roadmap.md for full SKU-level detail and competitive comparison vs. Broadcom Taurus BCM83640.

2.3 Coherent DSP / DCI (Inphi lineage)

FamilyProcessCapacityReachStatus
Canopus16 nm400GDCILegacy ✓
Hercules7 nm400ZR / 600GDCIProduction ✓
Orion5 nm TSMC800ZR / 800ZR+120 km unrep / 400 km repeatedShipping (COLORZ 800) ✓
Electra / Libra (codenames)3 nm est.1.6T60–80 kmSampling H2 2026 ◐
3.2T coherent (unnamed)2 nm3.2TTBDSampling 2028+; POH-enabled ⚠

Marvell’s competitive moat in coherent is meaningfully wider than in PAM4: Broadcom has not historically shipped a coherent DSP at parity (one undisclosed program reportedly in design ◐). Acacia (Cisco-acquired) is the only credible peer. ✓

2.4 Custom AI Silicon (xPU) — Cavium-origin custom team

Marvell does not disclose customer names in SEC filings, but five hyperscaler programs have been confirmed via press release, third-party reporting, or executive commentary:

CustomerProgramConfirmed ByStatus
AWSTrainium 2 (T2)AWS re:Invent 2024 keynote; Marvell Q3 FY26 earnings callVolume production ✓
AWSTrainium 3 (T3)Marvell Q4 FY26 earnings callRamping FY27 ✓
AWSTrainium 4 (T4) — “next-gen”Matt Murphy, Q3 FY26 callDevelopment ◐
MicrosoftMaia (Maia 100 / 200 — naming uncertain)Microsoft Ignite 2024 keynote; Reuters reportingVolume / next-gen ◐
GoogleAxion Arm CPUGoogle Cloud Next 2024 + 2025 keynotesProduction ✓
GoogleTPU v8i (rumored inference variant alongside Broadcom-owned training TPU)TheNextWeb reporting (2026) — talks underway, not confirmed in Marvell IRPre-announce ⚠
MetaArke / next-gen DPUMarvell Custom AI Investor Event Jun 17 2025; CRN reportingMulti-billion-dollar program ◐

Sources:

TAM: At the June 2025 Custom AI Investor Event, Marvell raised the data-center TAM to $94B by CY2028, with $55.4B from custom accelerated compute ($40.8B custom xPU + $14.6B xPU-attach). ✓

2.5 Switching (Innovium lineage)

GenerationProcessCapacityPortsStatus
Teralynx 716 nm12.8T32× 400GProduction (Cisco, hyperscaler) ✓
Teralynx 87 nm25.6T32× 800GLimited deploy ◐
Teralynx 105 nm TSMC51.2T64× 800G; homegrown 112 Gb/s PAM4 SerDesVolume from 2024-07-25 ✓
Teralynx 102.4T3 nm est.102.4T64× 1.6T or 128× 800GSampling H1 2026 (per Marvell guidance) ◐
115 Tb/s UALink switch3 nm est.115TUALink scale-upAnnounced Apr 2025 IAD; H2 2026 ◐

The 115 Tb/s UALink switch is critical: it’s Marvell’s stated entry into the scale-up domain currently dominated by Nvidia NVLink, and complements the Celestial AI Photonic Fabric on the optical side. ✓

2.6 Photonic Fabric / Optical Scale-Up (Celestial AI lineage)

Three product blocks:

  • OMIB (Optical Multi-chip Interconnect Bridge) — chiplet-to-chiplet optical bridge that sits on the same substrate as the xPU and replaces electrical inter-chiplet links with optical at >25 Tb/s/mm² shoreline density. ◐
  • OCI (Optical Compute Interconnect) — chiplet-form optical I/O for direct attach to compute / memory chiplets. ◐
  • Photonic Fabric Switch — aggregator silicon for scale-up clusters (multi-rack). ◐

All three are pre-revenue as of Apr 2026; first revenue expected calendar 2027 with full ramp into FY28. Counterpoint Research models Photonic Fabric reaching ~$1B annualized run rate by CY2029, conditioned on at least two hyperscaler design wins. ◐

2.7 Modulator IP (Polariton lineage)

POH modulators close the modulator-bandwidth gap (>100 GHz, demonstrated 1 THz in lab) at sub-100 µm device length, with Vπ·L ≈ 40 Vµm. The integration target is 3.2T DSP-paired transceivers from 2027, then potentially scale-up Photonic Fabric variants beyond. See polariton_acquisition.md.

3. Process Node and Packaging Mix at TSMC

3.1 Node mix across the portfolio (2026 snapshot)

NodeProductsVolume Status
16 / 28 nmLegacy storage controllers, OCTEON TX2Tail / cash-flow ✓
7 nmTeralynx 8, legacy Spica Gen1, COLORZ 600Mature ✓
5 nm TSMCSpica Gen2 800G DSP, Orion COLORZ 800ZR DSP, Teralynx 10 51.2T, OCTEON 10 familyVolume ✓
3 nm TSMC (N3E / N3P)Ara 1.6T DSP, AWS Trainium 3 (reported), Teralynx 102.4T (estimated), Microsoft Maia next-gen (reported)Ramping ✓ / ◐
2 nm TSMC (N2)Announced collaboration; future 3.2T DSP, future custom xPUPre-tapeout ✓

Source for 2 nm collaboration: Marvell + TSMC joint announcement, summarized in Futurum Group, “Marvell + TSMC Stimulating 2nm Accelerated Infrastructure Innovation.” ✓ URL: https://futurumgroup.com/insights/marvell-tsmc-stimulating-2nm-accelerated-infrastructure-innovation/

3.2 Advanced packaging at TSMC

Marvell is one of the largest non-Nvidia consumers of TSMC CoWoS advanced packaging in 2026. Customer-allocation reporting (Silicon Analysts, Q1 2026 Foundry Allocation) places Marvell at ~55,000 wafers of CoWoS through 2026, behind Nvidia (>200K) and AMD (~80K) but ahead of Broadcom-custom (~40K) and Intel/Apple. ◐ URL: https://siliconanalysts.com/analysis/foundry-allocation-status-q1-2026

Three CoWoS variants used:

  • CoWoS-S — Si interposer for HBM-attached AI ASICs (AWS Trainium, Microsoft Maia). ✓
  • CoWoS-L — local-Si-bridge for chiplet-heavy designs; the Celestial AI Photonic Fabric OMIB is qualified on CoWoS-L. ◐
  • CoWoS-R — RDL interposer for cost-down variants of optical modules and the 3D SiPho Engine. ◐

CoWoS lead times are ~50 weeks as of Q1 2026; Marvell’s allocation is locked through CY2027 per company guidance and TSMC’s customer-priority list. ◐

3.3 Why node + packaging matter for the platform thesis

The Inphi + Cavium + Innovium + Celestial + Polariton portfolio cannot exist on a single node. Marvell deliberately runs a heterogeneous mix because:

  • Optical DSP prefers leading-edge logic for power/lane-rate (3 nm Ara today, 2 nm next).
  • Custom xPU is leading-edge by definition (3 nm now, 2 nm next).
  • Switch runs one node behind logic (5 nm Teralynx 10) because SerDes maturity matters more than density.
  • Silicon photonics sits on TSMC’s specialty 90 nm SiPh process node — much trailing-edge — but with leading-edge electronics co-packaged via CoWoS.
  • POH modulators (post-Polariton) are a specialty CMOS-photonics process with EO-polymer post-processing; manufacturing partner not yet disclosed (likely a Swiss/German specialty fab today, expected to migrate into a TSMC-aligned flow post-close). ⚠

This heterogeneity is a moat: it requires foundry relationships, interposer expertise, and packaging engineering that pure-play DSP or pure-play switch competitors do not maintain.

4. The Pluggable / CPO / Scale-Up Optical Strategic Split

Marvell uniquely supports four distinct optical insertion points; the strategic question is how revenue mix evolves across them.

4.1 Pluggable optics (today’s revenue base)

QSFP-DD, OSFP modules with Marvell DSP inside (Spica Gen2, Ara, COLORZ). Hyperscalers buy from module ODMs (Coherent, Lumentum, Innolight, Eoptolink); Marvell sees DSP unit revenue not module revenue. Volume is 200 Gb/s/lane today, 400 Gb/s/lane with POH next.

4.2 Co-packaged optics (CPO) — emerging

Marvell 3D SiPho Engine announced Jan 6 2025; revenue ramp expected Q4 FY28. Architecturally targets custom xPU substrates (AWS Trainium, Microsoft Maia) where the customer accepts vendor lock-in. ✓ URL: https://investor.marvell.com/news-events/press-releases/detail/114/marvell-announces-breakthrough-co-packaged-optics-architecture-for-custom-ai-accelerators

4.3 Photonic Fabric scale-up — pre-revenue

Celestial OMIB / OCI / Photonic Fabric switch. Targets the NVLink replacement opportunity. First revenue 2027; meaningful ramp 2028+. ◐

4.4 Linear-drive (LPO/LRO) — passive observation

Marvell does not lead in linear-drive (LPO) module DSPs; the company’s stated position is that scaling raw modulator bandwidth (POH route) is the durable architecture. Competing vendors (Macom, Semtech, Maxim/Analog Devices) are more active in LPO. ✓

4.5 Strategic implications

The pluggable → CPO → scale-up trajectory matters because each step removes more of the addressable market from merchant pluggable optics module ODMs and concentrates value into Marvell’s silicon. Pluggable revenue per Tbps is ~$X; CPO captures roughly 1.3–1.5× more of the optics value chain into silicon; Photonic Fabric captures essentially all of it inside Marvell+packaging silicon. This is the single most important “earnings power expansion” thesis on the stock. See ../07_thesis/dsp_cannibalization_model.md.

5. Engineering Organization and Leadership Map

OrgLineageLeadership (Apr 2026)
Custom Compute (xPU, OCTEON)Cavium + organic MarvellSandeep Bharathi, President, Data Center Group ✓
Optical & Cloud ConnectivityInphiReports up through Sandeep Bharathi
Networking (Teralynx, UALink)InnoviumReports up through Sandeep Bharathi
Data Center Networking (scale-up)Celestial AIDave Lazovsky, EVP & GM, Data Center Networking ✓
Optical Engineering (CTO function)Inphi + organicRadha Nagarajan, SVP & Chief Technology Officer, Optical Engineering ✓
POH Modulator (post-close)PolaritonClaudia Hoessbacher (CEO Polariton) — retention TBD ◐

Source for leadership confirmations: Marvell leadership page (https://www.marvell.com/company/leadership.html) and OFC 2026 speaker assignments. ✓ URL: https://www.marvell.com/company/events/ofc-2026.html

6. Capital Allocation Backdrop for the Platform

Recent transactions stacked:

YearDealHeadline value
2018Cavium$6.0B
2019Aquantia$452M
2021Inphi~$10B
2021Innovium$1.1B
2025–26Celestial AI$3.25B base (up to $5.5B)
2026PolaritonNot disclosed; estimated $500M–1B ◐
Total~$21–22B over eight years

This is the largest cumulative M&A program in merchant semiconductor outside of Broadcom’s hyperscale software pivot. Marvell has funded it through a mix of equity (Inphi, Innovium, Celestial all included stock) and operating cash flow (~$1.6B FY26) plus targeted debt issuances. ✓ The Nvidia $2B equity investment announced March 2026 (NVLink Fusion partnership) provided incremental balance-sheet support during the Celestial close. ✓ URL: https://investor.marvell.com/news-events/press-releases/detail/1019/nvidia-ai-ecosystem-expands-as-marvell-joins-forces-through-nvlink-fusion

Implication: the platform is now broadly assembled; further M&A is more likely to be tuck-in (e.g., another modulator-material vendor, an Arm-CPU IP block) than transformational. ◐

7. Risk Map

  1. Hyperscaler concentration. Two customers (AWS + Microsoft) likely account for >50% of FY26 data-center revenue. ⚠ Specific concentration not disclosed in 10-K but implied by Q3 FY26 commentary regarding “two AI XPU programs in high-volume production.” ◐
  2. Broadcom in PAM4. Taurus BCM83640 sampling Mar 2026 challenges Ara’s first-mover lead. ✓
  3. Process-node bottleneck. 2 nm and CoWoS allocation are the binding constraints on FY27–28 supply. ◐
  4. POH manufacturing scale-up. Polariton volume manufacturing flow is unresolved; lab-to-fab transition is the single biggest technical risk in the 3.2T roadmap. ⚠
  5. Photonic Fabric uptake. Hyperscaler willingness to displace NVLink with Marvell scale-up optical is unproven; first-customer commitment will be the key leading indicator. ◐
  6. Geopolitical / China. Marvell exited the China-specific switch business in 2024; residual exposure is ~5–8% of revenue. ✓

8. Cross-References

  • optical_interconnect_roadmap.md — full PAM4 / coherent / CPO roadmap and SKU detail
  • polariton_acquisition.md — POH modulator deal mechanics
  • product_portfolio.md — segment-level revenue mix
  • foundry_relationships.md — TSMC / packaging deep-dive
  • patent_velocity.md — IP filing trajectory
  • ../03_ecosystem/customer_wallet_share.md — hyperscaler design-win matrix
  • ../07_thesis/dsp_cannibalization_model.md — pluggable → CPO → scale-up value migration

Sources (consolidated)

Cross-references