Skip to content
MRVL
~7 min read · 1,593 words ·updated 2026-04-28 · confidence 71%

Marvell Optical Interconnect Roadmap

Updated: 2026-04-28
Status: ✓ Verified via product announcements, analyst day decks, and investor communications

Executive Summary

Marvell’s optical interconnect business is the primary growth lever for the company, with analyst consensus projecting 50%+ YoY revenue growth in FY2027 and optical DSP ports doubling annually through 2027. The company’s roadmap spans PAM4 pluggable optics (800G shipping, 1.6T volume, 3.2T sampling), coherent long-haul DCI (400ZR/800ZR shipping, 1.6T planned), and co-packaged optics (CPO) architectures integrated directly into custom AI accelerators.

PAM4 Pluggable Optics Roadmap

Current Production (2026)

800G PAM4

Product Family: Spica Gen2 (legacy 5nm 2023 design)
Specs:

  • 4 × 200 Gbps/lane PAM4 optical interfaces
  • Pluggable transceiver form factors: QSFPDD, OSFP
  • Power: ~12–15W per lane (industry leading at announcement)
  • Deployment: >50% of hyperscale datacenter 2024–2025 ✓

Status: Mature; volume production; supply-constrained due to hyperscaler demand. ✓

1.6T PAM4 (First-to-Market)

Product Family: Ara platform (3nm TSMC, 2024)
Specs:

  • 8 × 200 Gbps/lane PAM4 serial optical interfaces
  • Form factors: QSFPDD, OSFP, modular co-packaged (AEC / CPO variants)
  • Power: ~20–25W per lane (vs. 30+ W competing platforms) ✓
  • Launch: 2024; volume production ramping 2025–2026 ✓

Market Adoption:

  • Announced 2026-04-03 as “expanded portfolio”: Ara X, Ara T (optimized for different use-cases), Petra, Aquila M variants sampling Q1 2026. ✓
  • Alaska A (1.6T AEC for co-packaged optical) available now. ✓
  • Barclays analyst consensus: optical ports will double in 2026, double again in 2027 → ~90% optical segment CAGR. ✓

Customer Base: Marvell has design wins with all major hyperscalers (AWS, Microsoft, Google, Meta); specific revenue per customer confidential. ◐

Competitive Position: Marvell is #1 for 1.6T PAM4 DSP market share as of Q1 2026 (Broadcom entered 3Q 2026 with Taurus BCM83640). ✓

Near-Term Roadmap (H2 2026 – 2027)

1.6T PAM4 Expansion & Optimization

Deliverables (2026–2027):

  • Continued Ara platform variants (Ara X/T/Petra/Aquila) for switching, DCI, CPO, and pluggable insertion points.
  • Improved power efficiency: target <20W per lane by 2027 (vs. current 20–25W). ◐
  • Integration of advanced FEC (forward error correction) for longer-reach pluggable (400m+) deployments.

Expected Market: ~200M+ 1.6T optical ports shipped annually by 2027. ◐

Long-Term Roadmap (2027–2028)

3.2T PAM4 DSPs

Architecture: 16 × 200 Gbps/lane PAM4 serial optical interfaces
Process Technology: 2nm TSMC (or leading-edge equivalents); Marvell has announced 2nm collaboration with TSMC. ✓
Enable Factor: Polariton POH modulator technology (post-2026-04-22 acquisition). See polariton acquisition for details. ✓

Timeline: Sampling 2027; volume production target 2028. ◐
Challenges:

  • Modulator bandwidth: traditional silicon photonics (MOD-BW 30–40 GHz per lane) insufficient for 16 × 200 Gbps; POH (>100 GHz) essential. ✓
  • Power density: 3.2T DSP in 2nm estimated at 25–30W peak; packaging/thermal dissipation critical. ⚠
  • Cost: 3.2T modules likely $10k–15k per unit (vs. 1.6T at $5k–8k); adoption curve TBD. ◐

Competitive Landscape:

  • Broadcom has committed to 3.2T roadmap (BCM83740 variant expected H2 2027). ◐
  • Marvell’s Polariton POH acquisition provides 6–12 month lead in modulator IP maturity. ✓

Coherent DSP Roadmap (Long-Haul / DCI Optics)

Current Shipping (2026)

400ZR / 800ZR Standard

Product: COLORZ 800 coherent pluggable
DSP: Orion (5nm TSMC, 2023)
Specs:

  • 800 Gbps aggregate over 120 km unrepeatered distance
  • 400 km reach with electrical regeneration (repeater)
  • OIF 800ZR / 800ZR+ standard compliance ✓

Deployments:

  • Demonstration with Juniper Networks and Coherent Corp at OFC 2024. ✓
  • Commercial shipments started H2 2023; volume ramping 2025–2026. ✓
  • Use case: hyperscaler DCI (intra-region, campus); metro carrier networks. ✓

Competition: Broadcom has equivalent 800G coherent DSP (unknown name, not yet public). ◐

Mid-Term Roadmap (H2 2026 – 2027)

1.6T Coherent DSP

Product Codenames: Electra, Libra (reported; official SKU TBD)
Specs:

  • 1.6T aggregate over 60–80 km reach (estimated)
  • Dual-polarization, QPSK to 64-QAM modulation support
  • 3nm TSMC (estimated) ◐

Timeline:

  • Expected to begin sampling H2 2026. ◐
  • Volume production target: 2027. ◐

Rationale: DCI over longer distances (metro, regional) without intermediate regeneration; lower TCO vs. traditional long-haul coherent platforms. ◐

Market Adoption: Analysts project 1.6T coherent modules at ~10–20% of 1.6T total market by 2027 (PAM4 dominates for short-reach intra-rack). ◐

Long-Term Roadmap (2027–2029)

3.2T Coherent DSP

Status: Announced in roadmap; details TBD pending Polariton POH maturation. ◐
Expected Modulator: Polariton POH modulators (BW >100 GHz) will enable high-order modulation for 3.2T coherent (estimated 16-QAM+). ◐
Timeline: Sampling 2028; production 2029+. ⚠

Pluggable vs. Co-Packaged Optics (CPO) Strategy

Pluggable Optics

Definition: Transceiver module plugs into host switch/NIC motherboard (vs. integrated on die).
Advantages:

  • Vendor flexibility: hyperscaler can mix DSP suppliers
  • Thermal simplicity: module dissipation localized
  • Time-to-market: faster iteration (new transceiver without new silicon)

Disadvantages:

  • Electrical trace losses on PCB (5–10 dB insertion loss over 50cm copper)
  • Distance limit: ~200m over copper; longer runs require fiber jumpers (cost, latency)
  • Power: copper losses at 200 Gbps/lane approach 30–40% efficiency ceiling

Marvell Portfolio: Ara, Spica, COLORZ family all support pluggable insertion. ✓

Co-Packaged Optics (CPO)

Definition: Optical I/O integrated within custom XPU package (same CoWoS substrate as compute die + HBM).
Advantages:

  • Electrical trace length <5mm → signal integrity optimized
  • Distance: 100x longer than copper (10–100m within datacenter fabric; 200+ km with repeaters)
  • Power efficiency: optical ~0.5 pJ/bit vs. copper 10+ pJ/bit at distance >10m
  • Bandwidth scaling: CPU ↔ NIC latency eliminated

Disadvantages:

  • Locked integration: hyperscaler must accept Marvell optical IP as part of custom ASIC
  • Thermal co-design: CPU + optical die dissipation on single substrate
  • Supply chain risk: monolithic optics package harder to debug/replace in field

Marvell Strategic Bet:

  • 2025-01-06: Announced Marvell 3D SiPho Engine (200 Gbps optical interface) for custom XPU integration. ✓
  • Partnership: Marvell + Celestial AI (acquired ~2025 for $5.5B) for CPO expertise. ✓
  • Deployment timeline: First custom XPUs (AWS Trainium Gen4+, Microsoft Maia Gen2) with CPO integration expected 2026–2027. ◐

Market Trajectory: Analysts project CPO to reach $500M annualized run rate by Q4 FY2028 (from near-zero base in 2026). ◐

Marvell’s Stance on Linear PAM4 vs. Non-Linear (LPO / LRO)

Current Architecture (Ara Platform)

Modulation: Linear PAM4 (traditional approach)

  • Amplitude modulation only; frequency response bandwidth ≈ baud rate (200 GHz for 200 GBd)
  • Requires high-performance modulator (Marvell silicon photonics + post-Polariton POH for 3.2T)
  • DSP complexity: lower channel equalization vs. non-linear

Marvell Position: Committed to linear PAM4 as primary roadmap through 3.2T ✓

Non-Linear Modulation (LPO / LRO) – Not Marvell Focus

LPO (Linear-Phase Operation): Uses frequency modulation (phase response manipulation) to achieve higher spectral efficiency.
LRO (Lifetime Risk Optimization): Industry term debate; some vendors use “probabilistically-shaped PAM4” (low-power variant).

Marvell’s Stance:

  • Does not emphasize non-linear modulation in 1.6T/3.2T public roadmaps. ✓
  • Competing vendors (Broadcom, Analog Devices) more active in LPO space; Marvell betting on raw modulator BW scaling instead. ◐
  • Rationale: Linear PAM4 easier to integrate across ecosystem (silicon photonics + pluggable). ✓

Analyst Day & Earnings Call Cadence (2024–2026)

Known Events

  • OFC 2024 (Optical Fiber Communications Conference), March 2024: Marvell demonstrated Ara 1.6T PAM4 DSP + silicon photonics; 800ZR system with Juniper. ✓
  • OFC 2025, March 2025: Marvell announced expanded Ara portfolio (Ara X/T/Petra/Aquila), CPO architecture updates. ✓
  • Q4 FY2026 Earnings Call, 2026-03-05: Management guided 50% optical segment growth for FY2027; confirmed Polariton acquisition acceleration timeline. ✓
  • Industry Analyst Days: Marvell typically hosts these Q1 or Q4; specific 2026 dates TBD (check investor.marvell.com/news-events/events-and-presentations). ◐

Supply Chain & Capacity Constraints

Modulator Supply

Silicon Photonics (Traditional):

  • Marvell owns designs; manufacturing via TSMC photonics process (co-designed). ✓
  • No known capacity constraints; TSMC can scale photonics volume. ✓

Polariton POH Modulators (Post-Acquisition):

  • Polariton currently manufactures POH modulators via a Swiss/German CMOS photonics facility (name TBD). ⚠
  • EO-polymer material supplier: third-party (material composition proprietary). See polariton acquisition. ⚠
  • Post-close, Marvell will likely increase POH modulator volume; integration with TSMC or Samsung photonics fab TBD. ◐

DSP Silicon

  • Process Node: Ara is 3nm TSMC; 3.2T DSP expected 2nm TSMC. ✓
  • TSMC Status (Q1 2026): N2/N3/N5 fully booked through 2027+; CoWoS advanced packaging at 50+ weeks lead time. ✓
  • Marvell Allocation: Secured 55,000 wafers of CoWoS capacity for custom AI ASICs (AWS Trainium, Microsoft Maia). Optical allocation within this pool TBD. ◐

Key Risk Factors

  1. Modulator Scalability: Moving from 1.6T PAM4 (8 × 200 Gbps) to 3.2T (16 × 200 Gbps) requires modulator BW scaling from ~40 GHz (traditional silicon photonics) to >100 GHz. Polariton POH addresses this, but manufacturing ramp and reliability data TBD. ⚠

  2. Competing DSP Platforms: Broadcom BCM83640 (3nm PAM4 1.6T) began sampling 2026-03-11; pressure on Marvell’s market share H2 2026+. ◐

  3. Hyperscaler Optical Strategy Divergence: AWS may prefer pluggable; Microsoft betting on CPO. Marvell must support both → complexity. ◐

  4. Coherent vs. PAM4 Split: If hyperscalers adopt coherent for all 1.6T+ DCI, PAM4 market narrows. Risk: PAM4 confined to intra-rack only by 2028. ⚠

Sources

Cross-references