Snapshot
| Item | Detail | Confidence |
|---|---|---|
| Legal name | XConn Technologies Holdings, Ltd. | ✓ (per Wilson Sonsini Ex. 5.1 opinion, 8-K acc. 0001193125-26-055923) |
| HQ | San Jose, California, USA | ✓ |
| Founded | 2020 | ✓ (CB Insights / company comms; emerged from stealth Aug 2023) |
| Status | Acquired by Marvell Technology, Inc. — closed 2026-02-10 | ✓ (Marvell 10-K Note 16 Subsequent Events) |
| Pre-acquisition CEO | Gerry Fan (continuing role at Marvell post-close) | ✓ |
| Core product | Apollo / Apollo 2 — industry’s first hybrid CXL + PCIe switch chips | ✓ |
| Marvell deal value | ~$540M total = $280.0M cash + ~2.1M MRVL common shares | ✓ (10-K Note 16) |
| Form D 506(b) sale | $199,956,892 to 40 accredited investors (closed 2026-02-10) | ✓ (Form D acc. 0001835632-26-000002) |
| Investors (pre-MRVL) | Marvell (strategic), Vertex Holdings, Translink Capital, Montage Technology, Novatek, Glory Ventures, China Mobility Fund | ✓ (424B7 prospectus 2026-02-18) |
Founding History & Technology
XConn Technologies was founded in 2020 in San Jose, California by a team of interconnect-silicon veterans, several of whom had prior careers at Broadcom and Marvell Semiconductor. CEO Gerry Fan previously managed chip-design teams at both Broadcom and Marvell Semiconductor before founding XConn — making the 2026 acquisition something of a “homecoming” for the founding team.
The company emerged from stealth at Flash Memory Summit (Santa Clara) in August 2023, debuting the XC50256 — the industry’s first and only hybrid CXL 2.0 + PCIe Gen 5 switch chip on a single piece of silicon. The Apollo product line evolved as follows:
| Generation | Standards | Status (at MRVL close) |
|---|---|---|
| Apollo (XC50256) | CXL 2.0 + PCIe Gen 5 hybrid | Production |
| Apollo 2 | CXL 3.1 + PCIe Gen 6 hybrid | Sampling |
The fabric architecture supports multi-level switching and flexible topology (mesh, dragonfly, 3D torus), enabling cache-coherent connectivity extended across racks — a capability Marvell now positions as the foundation of its UALink scale-up switch roadmap (Marvell 10-K, Item 1).
Sources:
- ✓ XConn Technologies Debuts Industry’s 1st Hybrid CXL 2.0 and PCIe Gen 5 Switch — HPCwire
- ✓ XConn Apollo 2 unveiling — DCD
- ◐ CB Insights XConn profile
Pre-Acquisition Funding
XConn remained privately funded with no publicly disclosed Series funding rounds. The 2026-02-18 424B7 resale prospectus identifies the cap table at closing via the selling-securityholder list (registering 2,116,573 MRVL shares for resale):
| Holder | Shares (MRVL) | Notes |
|---|---|---|
| Yan Fan | 513,845 | Largest individual holder; presumed founder/family |
| Translink Capital Partners V, L.P. | 336,628 | US/Asia bridge VC |
| Montage Technology Holdings Co. Ltd. | 286,053 | Chinese-listed (688008.SS) chip company |
| Novatek Investment Corporation Limited | (not separately disclosed) | Affiliate of Novatek Microelectronics (TW) |
| Glory Ventures Investments Fund LP | (not separately disclosed) | China-based growth fund |
| China Mobility Fund, L.P. | (not separately disclosed) | China-based VC |
| (other holders) | (residual) |
Source: ✓ 424B7 selling-shareholder list — Feb 18 2026 (via stocktitan summary)
The cap-table mix (significant Asian growth-VC and Chinese-listed strategic ownership) is notable but did not materially encumber the deal.
Marvell Acquisition — Deal Mechanics
Announcement & closing
- Announced: 2026-01-06 (Marvell IR press release #1004)
- Closed: 2026-02-10 (Marvell FY2026 10-K Note 16 — Subsequent Events)
Consideration (10-K-confirmed, supersedes press-release shorthand)
- Cash: $280.0M paid at close
- Equity: ~2.1M MRVL common shares issued (Form D 506(b) reports $199,956,892 sold value)
- Headline value: ~$540M (60% cash / 40% stock per CEO Murphy’s announcement comments)
- Earnouts: None disclosed (contrast with Celestial AI which has revenue-milestone earnouts through FY2029)
Strategic rationale (per Marvell 10-K Item 1)
“XConn’s advanced fabric architecture, [is] built on an ultra-latency fabric architecture that supports both multi-level switching and flexible fabric topology (mesh, dragonfly, 3D torus) enabling cache-coherent connectivity extended across racks.”
“[We have] expanded our portfolio to include a complete suite of PCIe and CXL connectivity solutions, spanning both re-timers and high-performance switches.”
Revenue contribution (guidance)
| Period | Run-rate / contribution |
|---|---|
| Q3 FY2027 | First revenue contribution |
| Q4 FY2027 | $50M annualized run-rate |
| FY2028 | ~$100M revenue contribution |
Source: ✓ Marvell Completes Acquisition of XConn Technologies
EDGAR / 8-K disclosure path — materiality finding
Marvell did NOT file an Item 1.01 / 2.01 acquisition 8-K for XConn. This is a deliberate materiality call: at ~$540M, the deal is ~0.4% of MRVL’s ~$130B market cap and below MRVL’s 8-K Item 1.01/2.01 materiality threshold. Public-disclosure path was instead:
| Filing | Date | Acc. No. | Purpose |
|---|---|---|---|
| Press release (issuer wire) | 2026-01-06 | (n/a) | Voluntary announcement of definitive agreement |
| Press release (closing) | 2026-02-10 | (n/a) | Voluntary announcement of close |
| S-8 | 2026-02-10 | 0001193125-26-044970 | Register Marvell shares assumed under XConn employee equity-comp plans |
| 8-K (Item 8.01 + 9.01) | 2026-02-18 | 0001193125-26-055923 | Filed solely to attach Wilson Sonsini Ex. 5.1 legal opinion supporting the resale prospectus |
| 424B7 | 2026-02-18 | 0001193125-26-055916 | Resale prospectus supplement registering 2,116,573 shares for selling securityholders |
| Form D (Reg D 506(b)) | 2026-02-25 | 0001835632-26-000002 | Notice-only of the 40-investor private placement of $199,956,892 in equity merger consideration |
| 10-K Note 16 | 2026-03-11 | 0001835632-26-000011 | First 10-K disclosure of full deal terms ($280M cash + 2.1M shares) |
Bottom line — Lead 1 resolution: ⚠ “Exempt-offering closed without 8-K disclosure” is the correct framing. Marvell has not filed and is not expected to file an Item 1.01/2.01 8-K covering the XConn deal — the deal is below the issuer’s materiality threshold and Marvell elected to disclose via the S-8 + resale-prospectus + Form D + 10-K-Note-16 channel instead. Full-text EDGAR search (q=XConn forms=8-K dateRange=2026-02-01..2026-04-29) returns only two XConn-mentioning 8-Ks (Feb 6 and Feb 18), both of which are Item 8.01 cover-pages for Wilson Sonsini legal opinions on shelf-prospectus issuances — not substantive deal disclosures.
Sources:
- ✓ EDGAR full-text search — XConn / 8-K / 2026-02-01..2026-04-29 — 2 results, both EX-5.1 cover-pages
- ✓ Marvell FY2026 10-K Note 16 — Subsequent Events
Regulatory considerations
CFIUS
- No CFIUS filing disclosed in any Marvell EDGAR filing or press release.
- XConn is US-incorporated (Delaware/California) with significant Asian (Taiwanese, Singaporean, Chinese-listed) growth-VC ownership in its cap table. CFIUS is most likely to scrutinize foreign-owned acquirers of US targets — here both acquirer and target are US-domiciled, so a mandatory filing was not triggered.
- Voluntary CFIUS notices for inbound clean-up of foreign minority interests in US targets are infrequent in the chip M&A bar, especially below $1B headline size, and there is no public indication Marvell pursued one.
Export control / BIS
- CXL/PCIe switch silicon is not currently an EAR/ECCN-controlled product class targeted by US-China advanced-chip rules (those rules center on AI accelerators, advanced HBM, and lithography tooling).
- No license-related disclosure surfaces in MRVL’s 10-K risk factors specific to XConn product lines.
Integration trajectory
Per the Marvell 10-K and integration commentary:
- UALink scale-up switch team augmentation — XConn engineering becomes nucleus of MRVL’s UALink (Ultra Accelerator Link) scale-up switch roadmap.
- Switch portfolio completion — combined with prior Marvell PCIe re-timer assets, MRVL now spans PCIe/CXL re-timers + switches end-to-end.
- TSMC process roadmap — XConn designs migrate to MRVL’s TSMC 2nm/1.4nm allocation for next-generation switch silicon.
- CEO Gerry Fan continuity — Fan publicly attested to the strategic fit at announcement: “Marvell brings cutting-edge SerDes technology, a leading process roadmap, deep hyperscale customer relationships.”
Cross-references
- m and a history — XConn entry in deal history
- legal contingencies — Form D #2 (XConn) reconciliation
- timeline — 2026-02-10 close milestone
- edgar full catalog — Form D / 8-K / S-8 entries
- celestial ai — sister Feb 2026 acquisition (different materiality treatment — Celestial got Item 1.01/2.01/3.02 8-Ks)
Outstanding questions
- ⚠ Does the XConn merger agreement contain customary post-close indemnity escrow? (Not disclosed; would appear in proxy/exhibit if material.)
- ⚠ Are there post-close non-compete covenants on the XConn co-founders (incl. Yan Fan, Gerry Fan) given their Broadcom/Marvell prior-employment background?
- ⚠ How are the Chinese-listed strategic holders (Montage, Novatek, Glory Ventures, China Mobility) handled for ongoing US-export-control compliance? Marvell’s outbound-customer screening for products embedding XConn IP may need revisiting.